A generally known method for stacking memory chips is the stacking of two unpackaged components. Here the first memory chip is placed directly on the substrate by applying solder bumps made of solderable metal alloys onto the substrate metallization and the memory chip is electrically contacted to the substrate with its active side down (face-down) by means of a suitable bonding process. The second, upper memory chip is mounted mechanically with its active side up (face-up) on the back side of the lower memory chip. Electrical contact of the upper memory chip with the substrate is achieved by means of wire bond connections.
Since the bond pads of memory chips are arranged centrally and the electrical connections of each bonding row of the upper memory chip must be made on the same side as that of the lower memory chip, a particular disadvantage of this simultaneously face-up and face-down arrangement of memory chips with double and multiple rows of bond pads is the necessity to cross-wire bond connections in order to electrically contact the upper memory chips to one another, whereby wire bond connections up to 10 mm in length may be required. Since it is necessary to prevent both contact and mutual thermal and electrical influences of the wire bond connections, numerous technological problems result regarding the process and regarding the equipment.
Testing and burn-in can be done only after the electrical contacting of the two memory chips, and thus only after the memory arrangement is finished, by contacting the landing pads on the substrate with probes and applying alternating signals. Devices recognized as defective during the production process and the tests go into the rework loop. Testing only after production of the stack arrangement leads to a markedly higher loss rate and thus a considerably higher rework expense than usually occurs in the testing of individual components.
An additional disadvantage of this solution lies in the handling of the individual memory chips as stack components, which leads to high requirements in the production process, particularly with respect to positioning precision, orientation of the chips parallel to the substrate, and the temperature profiles of chip and substrate.